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Freescale Semiconductor Technical Data
Document order number:
MC33897 Rev 11.0, 12/2005
Single Wire CAN Transceiver
The 33897 Series provides a physical layer for digital communications purposes using a Carrier Sense Multiple Access/ Collision Resolution (CSMA/CR) data link operating over a single wire medium. This is more commonly referred to as Single Wire Controller Area Network (CAN). The 33897 Series operates directly from a vehicle's 12 V battery system or a broad range of DC-power sources. It can operate at either low or high (33.33 kbps or 83.33 kbps) data rates. A highvoltage wake-up feature allows the device to control the regulator used in support of the MCU and other logic. The device includes a control terminal that can be used to put the module regulator into Sleep mode. The presence of a defined wake-up voltage level on the bus will reactivate the control line to turn the regulator and the system back on. The device complies with the GMW3089v2.4 General Motors Corporation specification. Features * * * * * * * * Waveshaping for Low Electromagnetic Interference (EMI) Detects and Automatically Handles Loss of Ground Worst-Case Sleep Mode Current of Only 60 A Current Limit Prevents Damage Due to Bus Shorts Built-In Thermal Shutdown on Bus Output Protected Against Vehicular Electrical Transients Undervoltage Lockout Prevents False Data with Low Battery Pb-Free Packaging Designated by Suffix Code EF
33897/A/B/C/D
SINGLE WIRE CAN TRANSCEIVER
D SUFFIX EF (Pb-FREE) SUFFIX 98ASB42565B 14-TERMINAL SOICN
EF (Pb-FREE) SUFFIX 98ASB42564B 8-TERMINAL SOICN
ORDERING INFORMATION
Device MC33897D/R2 MC33897EF/R2 MC33897AD/R2 MC33897AEF/R2 *MC/PC33897CEF/R2 MC33897BEF/R2 *MC/PC33897DEF/R2
* Recommended device for all new designs
Temperature Range (TA)
Package
14 SOICN - 40C to 125C
8 SOICN
Power Source VCC Voltage Regulator EN
Battery
VBATT VCC CNTL TXD RXD MCU MODE0 MODE1 GND 4 BUS LOAD SWC BUS
33897/A/C
Figure 1. 33897/A/C Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
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(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
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DEVICE VARIATIONS
VCC
Battery
VCC TXD RXD MCU
VBATT
BUS LOAD
SWC BUS
MODE0 MODE1
GND
33897B/D
Figure 2. 33897B/D Simplified Application Diagram
DEVICE VARIATIONS
Table 1. Device Variations
Part No. 33897 33897A Load Voltage Sleep Mode 1.0 V Max 0.1 V Max * * * * 33897B 0.1 V Max * * * * *33897C 0.1 V Max * * * *33897D 0.1 V Max * * * * Other Significant Differences 14-Terminal Package 14-Terminal Package Removes diode drop during Sleep Mode May not detect Loss of Ground under certain module characteristics. 8-Terminal Package Removes diode drop during Sleep Mode Does not include the CNTL terminal May not detect Loss of Ground under certain module characteristics. 14-Terminal Package Removes diode drop during Sleep Mode Effectively detects Loss of Ground 8-Terminal Package Removes diode drop during Sleep Mode Effectively detects Loss of Ground Does not include the CNTL terminal 2, 3, 4, 6, 7 10,12, 14 7 2, 3, 4, 6, 7 10,12, 14 See Page 7 7
*Recommended device for all new designs
33897/A/B/C/D
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Analog Integrated Circuit Device Data Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
TXDBus DRVR TX BUS DRVR
MODE0 MODE1
HV WU E n HVWU Enable
Mode Mode Co ntrol Control
Wa ve Sha ping E n Waveshaping Enable TX Dat Data TXD a Disab le Disable
BUS
Bus RCVR BUS RCVR
HV WU Detect HVWU De t RX Dat a RXD Data Disab le Disable
TXD RXD
Undervoltage Detect Timer OSC Load Switch
VBATT BAT
Timers
LOAD
GND CNTL CNTL*
*CNTL terminal is present on 33897/A/C only.
Figure 3. 33897/A/B/C/D Simplified Internal Block Diagram
33897/A/B/C/D
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TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
33897/A/C
GND TXD MODE0 MODE1 RXD NC GND
1 2 3 4 5 6 7 14 13 12 11 10 9 8
GND NC BUS LOAD VBATT CNTL GND TXD MODE0 MODE1 RXD
1 1 2 2 3 3 4 4
33897B/D
88 77 66 55
GND BUS LOAD VBATT
Figure 4. 33897/A/B/C/D Terminal Connections
Table 2. Terminal Definitions A functional description of each terminal can be found in the Functional Terminal Description section, begining on page 12.
33897/A/C Terminal 1, 7, 8, 14 2 3, 4 5 6, 13 33897B/D Terminal 8 1 2, 3 4 - Terminal Name GND TXD MODE0, MODE1 RXD NC Formal Name Ground Transmit Data Mode Control Receive Data No Connect Definition Electrical Common Ground and Heat removal. A good thermal path will also reduce the die temperature. Data input here will appear on the BUS terminal. A logic [0] will assert the bus, a logic [1] will make the bus go to the recessive state. These terminals control Sleep Mode, Transmit Level, and Speed. They have weak pulldowns. Open drain output of the data on BUS. A recessive bus = a logic [1], a dominant bus = logic [0]. An external pullup is required. No internal connection to these terminals. Terminal 13 can be connected to GND to allow the use of the 14-terminal or 8-terminal device. (1) 9 10 11 12 - 5 6 7 CNTL VBATT LOAD BUS Control Battery Load Bus Provides a battery-level logic signal. Power input. An external diode is needed for reverse battery protection. The external bus load resistor connects here to prevent bus pullup in the event of loss of module ground. This terminal connects to the bus through external components.
Notes 1. Module boards can be planned for the 14-terminal package and still use the 8-terminal package.
33897/A/B/C/D
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MAXIMUM RATINGS
MAXIMUM RATINGS
Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating Electrical Ratings Supply Voltage Input Logic Voltage RXD Terminal Voltage CNTL Terminal Voltage (33897/A/C only) ESD Voltage(2) Human Body Model All Terminals Except BUS BUS Terminal Machine Model Thermal Ratings Ambient Operating Temperature(3) Junction Operating Temperature Storage Temperature Junction-to-Ambient Thermal Resistance Peak Package Reflow Temperature During Solder Mounting (4) D Suffix EF (Pb-Free) Suffix TA TJ TSTG RJA TSOLDER 245 260 - 40 to 125 - 40 to 150 - 55 to 150 150 C C C C/W C VESD 2000 4000 200 VBATT VIN VRXD VCNTL - 0.3 to 40 - 0.3 to 7.0 - 0.3 to 7.0 - 0.3 to 40 V V V V V Symbol Value Unit
Notes 2. ESD testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), Machine Model (CZAP = 200 pF, RZAP = 0 ) 3. 4. When using the 8-terminal device, consider the power dissipation at a high operating voltage and maximum network loading at ambient temperatures exceeding 85C. Terminal soldering temperature limit is for 10 second maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device
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STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics Unless otherwise noted, characteristics noted under the following conditions: -40C TA 125C. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic GENERAL Quiescent Current Sleep 5.0 V VBATT 13 V (5) Awake with Transmitter Disabled 5.0 V VBATT 26.5 V Awake with Transmitter Enabled 5.0 V VBATT 26.5 V Undervoltage Shutdown Thermal Shutdown (6) 5.0 V VBATT 26.5 V Thermal Shutdown Hysteresis (6) 5.0 V VBATT 26.5 V LOGIC I /O, MODE0, MODE1, TXD, RXD Logic Input Low Level (MODE0, MODE1, and TXD) 5.0 V VBATT 26.5 V Logic Input High Level (MODE0, MODE1, and TXD) 5.0 V VBATT 26.5 V Mode Terminal Pulldown Current (MODE0 and MODE1) Terminal Voltage = 0.8 V, 5.0 V VBATT 26.5 V Receiver Output Low (RXD) IIN = 2.0 mA, 5.0 V VBATT 26.5 V CNTL (33897/A/C ONLY) CNTL Output Low IIN = 5.0 A, 5.0 V VBATT 26.5 V CNTL Output High IOUT = 180 A, 5.0 V VBATT 26.5 V VOHCNTL VBATT - 0.8 - VBATT VOLCNTL - - 0.8 V V VOL - - 0.45 IPD 10 - 50 V VIH 2.0 - - A VIL - - 0.8 V V TSDHYS 10 - VBATTUV TSD 150 - 20 C IQATEN IQATDIS IQSLP - - - 4.0 45 - - - 60 4.0 9.0 5.0 190 A mA mA V C Symbol Min Typ Max Unit
Notes 5. After tCNTLFDLY 6. Thermal shutdown causes the BUS output driver to be disabled. Guaranteed by characterization.
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STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued) Unless otherwise noted, characteristics noted under the following conditions: -40C TA 125C. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic LOAD LOAD Voltage Rise (7) Normal Speed and Voltage Mode, Transmit High-Voltage Mode, Transmit High-Speed Mode IIN = 1.0 mA, 5.0 V VBATT 26.5 V Sleep Mode 33897, IIN = 7.0 mA 33897A/B/C/D IIN = 7.0 mA (8) Loss of Battery IIN = 7.0 mA LOAD Leakage During Loss of Module Ground (9) 0.0 V VBATT 18 V BUS Passive Out BUS Leakage Passive In 0.0 V VBATT 26.5 V, -1.5 V VBUS < 0 V Active In 0.0 V VBATT 26.5 V, 0 V < VBUS 12.5 V BUS Leakage During Loss of Module Ground (10) 0.0 V VBATT 18 V High-Voltage Wake-up Mode Output High Voltage 12 V VBATT 26.5 V, 200 RL 3332 33897 33897A/B/C/D 5.0 V VBATT < 12 V, 200 RL 3332 VHVWUOHF VHVWUOHO 9.7 9.9 Lesser of VBAT - 1.5 or 9.7 VOHHS 4.2 - 5.1 V VNOHF VNOHO 4.4 Lesser of VBATT - 1.6 or 4.4 - 0.2 IBSC -350 - - 150 - - 5.1 Lesser of VBATT or 5.1 V - 0.2 mA - - 12.5 12.5 VBATT ILEAK ILKAI IBLKLOG -5.0 -5.0 -10 - - - 5.0 5.0 10 V A ILDLEAK 0.0 - - 90 A VLDRISE V Symbol Min Typ Max Unit
- - - -
- - - -
0.1 1.0 0.1 1.0
High-Speed Mode Output High Voltage 8.0 V VBATT 16 V, 75 RL 135 Normal Mode Output High Voltage 6.0 V VBATT 26.5 V, 200 RL 3332 5.0 V VBATT < 6.0 V, 200 RL 3332
V
BUS Low Voltage 5.0 V VBATT 26.5 V, 200 RL 3332 Short Circuit BUS Output Current Dominant State, 5.0 V VBATT 26.5 V
VOL
Notes 7. GMW3089V2.4 specifies the maximum load voltage rise to be 0.1 V whenever module battery is intact, including when in Sleep mode. The maximum load voltage rise of 1.0 V in Sleep mode is a GM-approved exception to GMW3089V2.4. 8. 33897A/B/C/D remove diode drop during Sleep mode. 9. LOAD terminal is at system ground voltage. 10. BUS terminal is at system ground voltage 33897/A/B/C/D
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STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued) Unless otherwise noted, characteristics noted under the following conditions: -40C TA 125C. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic BUS (continued) Input Threshold Awake 5.0 V VBATT 26.5 V Sleep 12 V VBATT 26.5 V Sleep 5.0 V VBATT < 12 V VBISO VBISF VBIA 2.0 6.6 Lesser of 6.6 V or VBATT - 4.3 - - - 2.2 7.9 Lesser of 7.9 V or VBATT - 3.25 V Symbol Min Typ Max Unit
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DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics Unless otherwise noted, characteristics noted under the following conditions: -40C TA 125C. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic BUS Normal Speed Rising Output Delay 200 RL 3332 , 1.0 s Load Time Constants 4.0 s Measured from TXD = VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V VBATT 26.5 V (11) Min Time to VBUSMOD = 1.0 V, 6.0 V VBATT 26.5 V (11) Max Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (11) Min Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (11) Normal Speed Falling Output Delay 200 RL 3332 , 1.0 s Load Time Constants 4.0 s Measured from TXD = VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V, 6.0 V VBATT 26.5 V (11) Min Time to VBUSMOD = 3.7 V, 6.0 V VBATT 26.5 V (11) Max Time to VBUSMOD = 1.0 V, VBATT = 5.0 V (11) Min Time to VBUSMOD = 2.7 V, VBATT = 5.0 V (11) High-Speed Rising Output Delay 75 RL 135 , 0.0 s Load Time Constants 1.5 s, 8.0 V VBATT 16 V Measured from TXD = VIL to VBUS as follows: Max Time to VBUS = 3.7 V (12) Min Time to VBUS = 1.0 V (12) High-Speed Falling Output Delay 75 RL 135 , 0.0 s Load Time Constants 1.5 s, 8.0 V VBATT 16 V Measured from TXD = VIH to VBUS as follows: Max Time to VBUS = 1.0 V (12) Min Time to VBUS = 3.7 V (12) Notes 11. VBUSMOD is the voltage at the BUSMOD node in Figure 7, page 14. 12. VBUS is the voltage at the BUS terminal in Figure 8, page 14. Symbol Min Typ Max Unit
t DLYNORMRO
2.0 - 6.3
s
t DLYNORMFO
1.8 - 8.5
s
t DLYHSRO
0.1 - 1.7
s
t DLYHSFO
0.04 - 3.0
s
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DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued) Unless otherwise noted, characteristics noted under the following conditions: -40C TA 125C. Voltages are relative to GND unless otherwise noted. All positive currents are into the terminal. All negative currents are out of the terminal.
Characteristic BUS (continued) High-Voltage Rising Output Delay 200 RL 3332 , 1.0 s Load Time Constants 4.0 s Measured from TXD=VIL to VBUS as follows: Max Time to VBUSMOD = 3.7 V, 6.0 V VBATT 26.5 V (13) Min Time to VBUSMOD = 1.0 V, 6.0 V VBATT 26.5 V (13) Max Time to VBUSMOD = 9.4 V, 12.0 V VBATT 26.5 V (13) High-Voltage Falling Output Delay 200 RL 3332 , 1.0 s Load Time Constants 4.0 s, 12.0 V VBATT 26.5 V Measured from TXD=VIH to VBUS as follows: Max Time to VBUSMOD = 1.0 V (13) Min Time to VBUSMOD = 3.7 V (13) Receiver RXD Receive Delay Time (5.0 V VBATT 26.5 V) Awake Receive Delay Time (BUS Rising to RXD Falling, 5.0 V VBATT 26.5 V) Sleep CNTL CNTL Falling Delay Time (5.0 V VBATT 26.5 V) (33897/A/C only) Notes 13. VBUSMOD is the voltage at the BUSMOD node in Figure 7, page 14. t CNTLFDLY 300 - 1000 ms t RDLYSL 10 - 70 t RDLY 0.2 - 1.0 s s 1.8 1.8 - - 14 14 2.0 2.0 2.0 - - - 6.3 6.3 18 s Symbol Min Typ Max Unit
t DLYHVRO
s
t DLYHVFO
33897/A/B/C/D
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Analog Integrated Circuit Device Data Freescale Semiconductor
TIMING DIAGRAMS
TIMING DIAGRAMS
tDLYNORMFO tDLYNORMRO
V IH
TXD
V IL V NOHF
V BUSMOD * V BIA
Bus
V BIA
V BUSMOD *
V IH
RXD
V IL tRDLY tRDLY
* VBUSMOD is the voltage at the BUSMOD node in Figure 7.
Figure 5. TXD, Bus and RXD Waveforms in Normal Mode
tDLYHSFO
TDLYHSRO
VIH TXD VIL VNOHF Bus VBIA VBUS *
VBUS * VBIA
VIH RXD VIL
tRDLY * VBUS is the voltage at the BUS terminal in Figure 8.
tRDLY
Figure 6. TXD, Bus and RXD Waveforms in High Speed Mode
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33897 Series is intended for use as a physical layer device in a Single Wire CAN communications bus. Communications takes place from a single terminal over a single wire using a common ground for a current return path. Two data rates are available, with the high rate used for factory or assembly line communications and the lower for actual system communications where the radiated EMI of the higher rate could be an issue. Two terminals control the mode of operation (sleep, lowspeed, high-speed, and high-voltage wake-up).
FUNCTIONAL TERMINAL DESCRIPTION
The 33897 Series is intended to be used with an MCU to control its operation and to process and generate the data for the bus.
RXD Data
The data received on the bus is translated to logic levels on this terminal. This terminal is a logic high when the bus is in the recessive state (near zero volts) and is logic low when the bus is in either the normal or high-voltage dominant state. This is an open-drain type of output that requires an external resistor to pull it up. When the device is in sleep mode, the output will be off unless a high-voltage wake-up level is detected on the bus. If the wake-up level is detected, the output will be driven by the data on the bus. If the level of the data returns to normal level, the output will return to off after a short delay unless a non-sleep mode condition is set by the MCU.
Ground Terminals (33897/A/C)
The four ground terminals are not only for electrical conduction, their number and locations at each of the four corners serve also to remove heat from the IC. The biggest benefit of this is obtained by putting a lot of copper on the PCB in this area and, if ground is an internal layer, by adding numerous plated-through connections to it with the largest diameter holes the layout can use.
TXD Data
The data driven onto the SWCAN bus is inverted from the TXD terminal. A "1" driven on TXD will result in an undriven (recessive) state (bus at near zero volts). When the TXD terminal is low, the output goes to a driven state. The voltage and waveshaping in the driven state is determined by the levels on the MODE0 and MODE1 terminals (refer to Table 6). Table 6. Mode Control Logic Levels
Logic Level Operation MODE0 0 0 1 1 MODE1 0 1 0 1 Sleep Mode High Voltage Wake-Up Mode High Speed Mode Normal Mode
LOAD Switch
This switch is on in all operating modes unless a loss of ground is detected. If this happens, the switch is opened and the resistor normally attached to its terminal will no longer pass current to or from the bus.
CNTL Output (33897/A/C Only)
This logic level signal is used to control a VCC regulator. When the output is low, the VCC regulator is expected to shutdown. This is normally used to shut down the MCU and all the devices powered by VCC when the IC is in sleep mode. This is done to save power. When the part is taken out of the sleep mode by the higher-than-normal bus voltage, this terminal is asserted high and the VCC regulator brings its output up to the regulated level. This starts the MCU, which controls the mode of the IC. The MCU must change the mode signals to non-sleep mode levels in order to keep this terminal from going low. There is a delay to allow the MCU to fully wake up and take control after the high-voltage signaling is removed before the level on this output returns low. After a delay time, even if the bus is at high voltage, the IC will return to sleep mode if both MODE terminals are low.
Mode Control
The MODE terminals control the transmitter filtering and BUS voltage and the IC sleep mode operation. Table 6 shows the mode versus the logic levels on MODE0 and MODE1. The MODE0 and MODE1 terminals have a weak pulldown in the IC so that in case the terminals are not driven, the device will enter the sleep mode. This is usually the situation as the MCU comes out of reset, before the driving signals have been configured as outputs.
33897/A/B/C/D
VBATT Input
This power input is not reverse battery protected and should use an external diode to protect it from damage owing to reverse battery if this protection is desired. The voltage drop of the diode must be taken into consideration when the operating range of the system is being determined. This
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM COMPONENTS
diode is generally used to protect the entire module from reverse battery and should be selected accordingly.
BUS I /O
This input / output may require electrostatic discharge (ESD) and /or EMI external circuitry. A set of components is
shown in the simplified application diagrams on page 15 of this datasheet. The value of the capacitor should be adjusted downward in direct proportion to the added capacitance of the ESD or EMI circuits. The series resistance of the inductor should be kept below 3.5 to prevent its voltage drop from significantly degrading system noise margins.
FUNCTIONAL BLOCK DIAGRAM COMPONENTS Timer OSC
This circuit generates a 500 kHz signal to be used for internal logic. It is the reference for some of the required delays.
TXD BUS DRVR
This circuit drives the BUS. It can drive it with the higher voltage wake-up signals when enabled by the Mode Control circuit. It can also provide waveshaping for reduced EMI or not provide it for the higher data rate mode. The actual data is received on TXD at CMOS logic levels, then translated by this circuit to the necessary operating voltages.
Timers
This circuit contains the timing logic used to hold the CNTL active for the required time after the conditions for sleep mode have been met. It is also used to keep the TXD driver active for a period of time after it has generated a passive level on the bus.
Undervoltage Detect
This circuit monitors internal operating voltage to assure proper operation of the part. If a low-voltage condition is detected, it sends a signal to disable the BUS RCVR and TXD BUS DRVR circuits. This prevents incorrect data from being put on the bus or sent to the MCU.
Mode Control
This circuit contains the control logic for the various operating modes and conditions required for the IC.
Load Switch
The LOAD switch provides a path for an external resistor connected to the BUS to be connected to ground. When a loss of ground is detected, this switch is opened to prevent the current that would normally be flowing to the ground from the module from going back through the load resistor and raising the bus level. The circuit is opened when the voltage between GND and VBATT becomes too low as would be the case if module ground were lost.
BUS RCVR
This circuit translates the levels on the BUS terminal to a CMOS level indicating the presence of a logic [0] or a logic [1]. It also determines the presence of a high-voltage wake-up (HVWU) signal that is passed to Mode Control and Timers circuits. An analog filter is used to "de-glitch" the highvoltage wake-up signal and prevent false exits from the sleep mode.
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BUS LOADING PARAMETERS FUNCTIONAL BLOCK DIAGRAM COMPONENTS
BUS LOADING PARAMETERS
VBATT 100 pF 1.0 k 47 H BUSMOD 6.49 k (n -1)
33897
BUS 6.49 k LOAD GND
CNOM = 100 pF + (n -1) 220 pF
R=
Note: The letter "n" represents the number of nodes in the system.
Figure 7. Transmitter Delays in Normal and Transmit High-Voltage Wake-Up Modes
33897
BUS 6.49 k LOAD GND 130 CNOM = (n) 220 pF R= 6.49 k (n -1)
Note: The letter "n" represents the number of nodes in the system.
Figure 8. Transmitter Delays in Transmit High-Speed Mode
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33897/A/C can be used in applications where the module includes a regulator that has the capability of going into Sleep mode by having an Enable terminal. See Figure 9. When the module's regulator is in sleep mode, the module is turned off. The module waits for a defined wake-up voltage
VCC Voltage Regulator EN
level on the bus. This wake-up voltage will activate the control line, which enables the regulator and turns the module back on. This 33897/A/C feature allows the module to be more energy efficient since the current consumption is significantly lowered when it goes into sleep mode.
Battery 100 pF 4.7 F
Power
Source 100 nF VBATT CNTL TXD RXD BUS
1.0 k 47 H SWC BUS 47 pF 6.49 k
VCC
10 k
2.7 k
MCU
MODE0 LOAD MODE1
GND
4
33897/A/C
Figure 9. 33897/A/C Typical Application Schematic The 33897B/D do not have a control terminal to enable the module's regulator. See Figure 10. The 33897B/D can be used in applications where board space is limited and there is no need for the module to have control over its regulator via the transceiver.
VCC
100 nF
Battery 100 pF VBATT 1.0 k 4.7 F
VCC
10 k
2.7 k TXD RXD BUS
47 H SWC BUS 47 pF 6.49 k
MCU
MODE0 LOAD MODE1
GND
33897B/D
Figure 10. 33897B/D Typical Application Schematic
33897/A/B/C/D
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important: For the most current Package revision, visit www.freescale.com and perform a Keyword Search on the "98A" drawing number below.
D SUFFIX EF (Pb-FREE) SUFFIX 14-TERMINAL SOIC NARROW BODY PLASTIC PACKAGE 98ASB42565B ISSUE H
33897/A/B/C/D
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS (CONTINUED)
PACKAGE DIMENSIONS (CONTINUED)
EF (Pb-FREE) SUFFIX 8-TERMINAL SOIC NARROW BODY PLASTIC PACKAGE 98ASB42564B ISSUE U
33897/A/B/C/D
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REVISION HISTORY
REVISION HISTORY
Revision 9.0
Date 5/2005
Description of Changes * * * * * * * * Converted to Freescale format Added A & B Versions Updated Device Variation Table, and Note "* Recommended device for all new designs" Added EF (Pb-Free) Devices, and higher soldering temperature Implemented Revision History page Updated Simplified Application Diagrams Updated Typical Application Schematic Added 33897C and D versions and Timing Diagrams
10.0
8/2005
11.0
12/2005
33897/A/B/C/D
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC33897 Rev 11.0 12/2005

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